A. Field of the Invention
The present invention relates generally to sample and hold phase locked loops and more particularly to an improved detector for indicating when the phase locked loop is out of the lock condition.
B. Description of the Prior Art
Phase locked loops are widely used in electronics communication systems for such application as frequency synthesis. A typical sample and hold phase locked loop suitable for frequency synthesis essentially consists of: a sample and hold phase detector for a divided voltage controlled oscillator signal, a low pass filter for receiving the output of the phase comparator, a VCO for receiving the output of the low pass filter, and a loop divider for dividing the VCO output and applying the divided signal to the phase comparator.
Basically, the phase comparator forms a difference signal by comparing the external reference signal and the divided VCO signal (loop pulse). The difference signal is passed through a low pass filter to obtain a DC control voltage (steering voltage) which controls the frequency of the VCO. When the frequency of the external reference signal and the frequency of the divided voltage controlled oscillator signal are substantially identical, the phase locked loop is said to be in the state of lock. Conversely when the external reference signal and the divided VCO signal differ in frequency by more than a predetermined amount or portion, the phase locked loop is said to be out of lock.
It is useful to determine when the phase locked look is in an out of lock condition to allow certain loop parameters to be changed so that the loop can acquire lock over a wider frequency range, or to prevent some function from operating until the loop has achieved the proper locked condition. A common problem with prior art out of lock detectors for sample and hold phase locked loops is that they cannot detect that the loop is still converging to the correct frequency while it is in the linear range of the phase detector.
One prior art out of lock detector for this type of phase locked loop is the frequency steering out of lock detector. This out of lock detection scheme basically consists of two digital phase detectors connected with other logic so as to compare the relative phases of the reference signal and the divided loop pulse. The frequency steering logic defines in lock as a condition where the the loop pulse rises anywhere in the 0.degree. to 180.degree. region of the reference signal. The out of lock command is generated whenever the loop pulse rises prior to the reference or when the reference falls before the loop pulse rises. This approach is relatively slow at detecting the out of lock condition especially in the situation in which the VCO frequency is too low, and is unable to detect a condition in which there is excessive reference feed through. A far more serious limitation of this method is that it cannot detect the condition in which the phase detector is in the linear range but the VCO is not at the exact required frequency.
Another type of prior art out of lock detection is the rail detection method. This type of out of lock detection is based simply on the fact that if, for example, three to eight volts DC is the useful steering voltage range of the synthesizer, any phase detector voltage higher or lower than these limits is unacceptable or out of lock. The rail detector can be built by using two comparators to compare the phase detector voltage to a high and low preset reference. With this technique an out of lock indication may not be generated if the synthesizer system is close to the desired frequency (i.e., in the linear range), or is beating at a very low frequency. Also, if the loop pulse is lost due to a malfunction, it would take a long time for an out of lock indication to be generated.